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September 20, 2011

DFI Technical Group Releases Preliminary DDR PHY Interface (DFI) 3.0 Specification



By Rajani Baburajan
TMCnet Contributor



The DDR PHY Interface (DFI) Technical Group announced the release of preliminary DFI 3.0 specification, the latest version of the pervasive industry specification that defines an interface protocol between DDR memory controllers and PHYs.

The DDR-PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface.

While the DFI specification is designed to be used by developers of both memory controllers and PHY designs, it does not place any restrictions on how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices.

"DFI has quickly become the dominant interface specification for DDR controllers and PHYs, and semiconductor companies are already specifying products to support the upcoming transition to DDR4," said John MacLaren, chairman of the DFI Technical Group, in a statement.

 "This new specification eases the integration of DDR4 memory controllers and PHYs, taking into account the complex power and performance challenges associated with implementing high-speed memory," MacLaren added.

With the new specification, developers can build chips that support the emerging DDR4 memory standard.

DFI 3.0 builds on the strong foundation of previous specifications. It now defines methods for interfacing to DDR4 devices with proposed data rates up to 3.2 Gbits/second per pin -- more than 50 percent faster than the current DDR3 standard -- and extends the low-power interface that was introduced with DFI 2.1, company officials said.

By accounting for frequency and power challenges at high speeds, the new specification helps ensure exceptional performance in systems using DDR4 memory, according to officials at the DFI Technical Group. The preliminary specification is available now for download at www.ddr-phy.org.

The new DFI specification is the result of collaborative work between the DFI Technical Group members including ARM Limited, Cadence Design Systems, Intel Corporation, LSI Corporation, Samsung Electronics, ST-Ericsson (News - Alert) and Synopsys. DFI interface is in use by hundreds of companies with 3100 downloads. DFI effort is supported by major DDR IP suppliers.


Rajani Baburajan is a contributing editor for TMCnet. To read more of Rajani's articles, please visit her columnist page.

Edited by Rich Steeves
 
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